Power gating is a technique to manage leakage power during the standby mode in low-power and high-speed integrated circuits (ICs). Conventional power gating techniques utilize transistor-based switches (e.g., sleep transistors) to shut down part of the circuit block and put it in idle mode. Sleep transistors help ICs manage power and thermal effects efficiently. The total power consumption of the ICs is comprised of static, dynamic, and short-circuit effects. The dynamic behavior has an exponential effect on the power dissipation, and as a result, it leads to a higher temperature injection in the circuit node. In the static mode, temperature has an exponential effect on the leakage current. This interdependence of power and thermal impacts makes an efficient power gating circuit a very critical requirement for integrated circuits and systems.
Conventional sleep transistor based power gating techniques utilize one of the three approaches as shown in FIGS. 1A-1C. The first approach, illustrated by FIG. 1A, employs high threshold voltage (high-Vt) transistors between the supply lines and the circuit to create virtual Vdd and Vss nodes at every cell that needs to be shut down or placed in a sleep mode. The high-Vt sleep transistors are implemented in the form of a “header switch” and a “footer switch” to isolate the virtual supply nodes from the actual supply lines, as shown in FIG. 1A. The second approach, illustrated by FIG. 1B, utilizes only a “header switch” by connecting a high-Vt transistor between the actual power rail and the virtual Vdd node. And the third approach, illustrated by FIG. 1C, utilizes only a “footer” switch.
All of the above approaches are used to lower subthreshold current leakage. Other conventional techniques include a reconfigurable sleep transistor technique, a negative bias temperature instability (NBTI) aware sleep transistor design, and a sleep transistor inserted as part of a 3T DRAM cell to reduce leakage power. In all of these conventional approaches, low-Vt transistors are used inside the logic circuits to ensure higher performance during the active mode of the circuit. High-Vt sleep transistors are placed between the logic circuits and the supplies to reduce leakage power during the standby period. These sleep transistors used as “header” and/or “footer” switches impose extra area, delay, and power overheads. Additionally, the design complexity involved with the implementation of transistors with different threshold voltages in the same circuit makes these design techniques less appealing. Moreover, the additional wiring required for the virtual nodes introduces unwanted resistor, inductor, capacitor (RLC) issues and IR-drops causing voltage variations.